RTL Design Engineer 5

Job Overview:

Requirement/Must Have:

• 10+ years of experience in RTL design using Verilog HDL.

Responsibilities:

• Responsible for RTL design using Verilog HDL for implementation and debug.
• Read and comprehend System on Chip level architectural specification.
• Write microarchitecture specification for new and modified functions.
• Responsible for linting and simulation of design.
• Work with synthesis and backend teams for physical implementation.

Qualification And Education:

• Bachelor's or Master's in Computer Engineering.